PRIORITIZED BUS REQUEST SCHEDULING MECHANISM FOR PROCESSING DEVICE

Patent №

US 6,499,090

Granted

2002-12-24

Filed 1999

Owner

INTEL CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09474010

A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.

AI hardwareG06F 13/1642G06F 13/18G06F 13/362G06F 12/0862

AI classification

AI hardware1.00
Machine learning0.02
Natural language0.01
Planning0.00
Knowledge representation0.00
Speech0.00
Evolutionary computation0.00
Vision0.00

Ownership

INTEL CORPORATION

assignment · 106800158

Assignors

HILL, DAVID L., BACHAND, DEREK T.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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