PROCESSOR CACHE SYSTEM WITH PARITY PROTECTION AND METHOD OF OPERATION

There is disclosed a cache memory for use in a data processor. The cache memory comprises a first static random access memory (SRAM) that receives up to N incoming bytes of data on an input bus and that stores the up to N incoming bytes of data in an N-byte addressable location. M incoming bytes of data may be written in each of the N-byte addressable locations during a write operation (where M may be less than N) and the M written bytes of data and N−M unwritten bytes of data are output from each N-byte addressable location on an output bus of the first SRAM during each write operation. The cache memory also comprises a parity generator coupled to the first SRAM that receives the M written bytes of data and the N−M unwritten bytes of data and generates at least one write parity bit associated with the M written bytes of data and the N−M unwritten bytes of data.