AN IC CHIP PLANNING METHOD BASED ON DYNAMIC PARALLEL GENETIC ALGORITHM AND SPECKLE MODEL

A chip planning method, tool and system for generating a population of gene strings representing floor plans for an integrated circuit, executing crossover on the strings to generate crossover child strings, executing mutation on the strings to generate mutated child strings, applying peristalsis operators to the strings to generate peristalsis child strings, and evaluating the child strings for inclusion in the population. The operators are peristalsis operators based on a speckle model. Dynamic control of migration rates and ranking is also executed, together with controlled race migration and immigration. Dynamic ratio control and optimisation of interconnecting area and pin assignment are also executed.