LOW POWER DIFFERENTIAL CONDUCTANCE-BASED LOGIC GATE AND METHOD OF OPERATION THEREOF

A logic gate and methods of operation and manufacturing thereof. In one embodiment, the logic gate comprises complementary first and second computational blocks having first and second sets of binary inputs, respectively. The first computational block develops an output binary digit that is a function of a weighted sum of a first set of input binary digits presented at the first set of binary inputs. The second computational block develops a complementary output binary digit that is a function of a weighted sum of a second set of input binary digits presented at the second set of binary inputs. The logic gate further comprises a cross-coupled differential load, including a first load circuit coupled to the first computational block and driven by the complementary output binary digit, and a second load circuit coupled to the second computational block and driven by the output binary digit.