ALLOCATION OF PROCESSOR BANDWIDTH BY INSERTING INTERRUPT SERVICING INSTRUCTIONS TO INTERVENE MAIN PROGRAM IN INSTRUCTION QUEUE MECHANISM

Patent №

US 6,662,297

Granted

2003-12-09

Filed 1999

Owner

INTEL CORPORATION (A CORP. OF DELAWARE)

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09474834

The method and apparatus feature detecting and prioritizing one or more interrupt service requests; inserting interrupt servicing instructions responsive to the interrupt service request into an instruction queue mechanism; and processing the instructions within the instruction queue mechanism including the inserted interrupt servicing instructions. The instruction queue mechanism may include an instruction cache and an instruction fetch unit for fetching instructions from the instruction cache, wherein the processing includes decoding the instructions into micro-opcodes and executing the micro-opcodes in one or more out-of-order execution units. Further features include retiring the executed micro-opcodes including those micro-opcodes representing the inserted interrupt servicing instructions to the instruction cache. Preferably, the criteria for interrupting the core processor include the priority of the interrupts and the capacity of the processor to allocate bandwidth to interrupt servicing. Most preferably, the prioritizing is dynamically responsive to changing allocation criteria, e.g. a current-usage model.

AI hardwareG06F 9/4812G06F 9/30174G06F 9/3802G06F 9/3836G06F 9/3854G06F 9/3856G06F 9/3858G06F 9/3861

AI classification

AI hardware0.98
Natural language0.00
Evolutionary computation0.00
Speech0.00
Machine learning0.00
Planning0.00
Vision0.00
Knowledge representation0.00

Ownership

INTEL CORPORATION (A CORP. OF DELAWARE)

assignment · 107580840

Assignors

BOOM, DOUGLAS D., GILBERT, MATTHEW M.

On an employer assignment, the assignors are typically the inventors.

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