CYCLE AND PHASE ACCURATE HARDWARE-SOFTWARE CONVERIFICATION

Cycle and phase accurate hardware-software coverification is disclosed. According to the present disclosure, “cycle accurate” or “phase-accurate” hardware-software coverification is performed while substantially maintaining a high speed for performing the coverification. System activities are divided into a “pre-compute” and a “post-compute” category. Those activities which fall in the pre-compute category are evaluated to ensure that updates to the state of the system are performed on a clock edge immediately following a change in system inputs affecting the state of the system. The state of the system is then updated on the same clock edge at which the pre-compute operation was performed. Those activities which fall in the post-compute category are then evaluated at the same clock edge on which the state of the system was updated. As a result of the post-compute operation, system outputs are timely generated while taking into account the change in the state of the system. The division of system activities into those requiring pre-compute and those requiring post-compute substantially maintains a relatively high speed of hardware-software coverification.