METHOD FOR CREATING STANDARD VHDL TEST ENVIRONMENTS

A method, a data structure, a computer program product and a computer for testing digital designs defining integrated circuits in a HDL before actually building the integrated circuits and, more specifically, for creating standard test environments for digital designs. One embodiment provides a method of creating an entity description for use in an automated testing environment, the entity description defining an entity of an integrated circuit in a hardware description language, the entity of the integrated circuit comprising at least one interface having a plurality of ports each associated with a pre-determined function. The method comprises, for at least one port of the plurality of ports, associating at least one indication of a specific procedure call with the at least one port, the specific procedure call defining the pre-determined function of the at least one port.