PROGRAMMABLE MULTI-STANDARD I/O ARCHITECTURE FOR FPGAS

Patent №

US 6,909,306

Granted

2005-06-21

Filed 2002

Owner

—

Lab

—

AI components

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

10246094

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The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards.

AI hardwareH03K 19/17748H03K 19/17744H03K 19/1778

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Cites (8)

Programmable multi-standard I/O architecture for FPGAsUS 6,392,437 · 2002 PROGRAMMABLE INPUT/OUTPUT CIRCUIT FOR FPGA FOR USE IN TTL, GTL, GTLP, LVPECL AND LVDS CIRCUITSUS 6,218,858 · 2001 ENHANCED FIELD PROGRAMMABLE GATE ARRAYUS 6,150,837 · 2000 FLEXIBLE FPGA INPUT/OUTPUT ARCHITECTUREUS 5,625,301 · 1997 PROGRAMMABLE LOGIC MODULE AND ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAY DEVICEUS 5,570,041 · 1996 PROGRAMMABLE LOGIC MODULE AND ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAY DEVICEUS 5,477,165 · 1995 PROGRAMMABLE LOGIC MODULE AND ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAY DEVICEUS 5,451,887 · 1995 INPUT/OUTPUT MODULE WITH LATCHESUS 5,017,813 · 1991

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