POWER REDUCTION MECHANISM FOR FLOATING POINT REGISTER FILE READS

A system and method for reducing power consumed by a floating unit performing iterative calculations in a loop through selectively inhibiting floating point register file reads. One or more source register address values are compared with one or more current values generated from a first iteration of a loop, and upon determining that one ore or more values in the source registers are the same as one or more current generated values, floating point register file reads of the equal values from the one or more source registers are inhibited. The current generated values from the first iteration of the loop are preferably held in one or more pipeline registers.