METHOD AND APPARATUS FOR PERFORMING EXTRACTION ON AN INTEGRATED CIRCUIT DESIGN

The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. For example, extracting the resistance from a straight section of interconnect wire may be performed by multiplying a known resistance per unit length by the length of the straight section of interconnect wire. For more complex extraction sub problems, machine learning is used to build models. In one embodiment, Support Vector Machines are constructed to extract the desired electrical characteristics.