AUTOMATIC RESISTANCE AND CAPACITANCE TECHNOLOGY FILE GENERATOR FOR MULTIPLE RC EXTRACTORS

A method for generating technology data files for use by at least one chip and circuit analysis tools begins by accepting a user analysis request for a specific chip and circuit analyses. The design automation tool required for the requested analysis is then selected. A standard, generic technology data file(TDF) is converted to a custom TDF specified for a given design analysis tool from a set of TDF formatting rules for the given design analysis tool. The chip coordinate references, process parameters and line segment layout data to be tested are extracted from a physical design data layout file. The line segment layout data of a standard wafer test site for the foundry/process selected is extracted from a circuit simulation model of the desired foundry/process. The design automation tool is executed using the foundry/process and line segment layout data as requested in the user analysis request. An analysis specified by said user analysis request with the selected design automation tool is executed using the foundry/process and line segment layout data of the standard wafer test site. The results of the analysis using the foundry/process and line segment layout data of the standard wafer test site are compared with the actual data describing the test site function. Reports are issued describing the success of the analysis.