Patent US 6,975,980

Patent №

US 6,975,980

Granted

Owner

Lab

AI components

1

planning

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

10172568

An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE Standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

PlanningG01R 31/3177G01R 31/318555G01R 31/318558G01R 31/318561G01R 31/318563G01R 31/318572

AI classification

Planning0.96
Knowledge representation0.03
AI hardware0.01
Natural language0.00
Vision0.00
Evolutionary computation0.00
Machine learning0.00
Speech0.00
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