TEST REGION LAYOUT FOR SHALLOW TRENCH ISOLATION

Patent №

US 7,002,177

Granted

2006-02-21

Filed 2003

Owner

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

10701824

A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

AI hardwareH01L 22/34H10P 74/277H01L 21/76229H10W 10/0143H10W 10/17

AI classification

AI hardware0.82
Vision0.37
Speech0.00
Knowledge representation0.00
Natural language0.00
Machine learning0.00
Planning0.00
Evolutionary computation0.00

Ownership

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

assignment · 146850479

Assignors

CHANG, WENG, LU, CHIH-CHENG, FU, CHU-YUN, JANG, SYUN-MING

On an employer assignment, the assignors are typically the inventors.

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