Patent №
US 7,099,998
Granted
2006-08-29
Filed 2000
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09539839
A method for reducing an importance level of a line in a memory of a cache. An instruction is provided to the cache, the instruction indicating that the line is a candidate for replacement. The importance level of the line may then be reduced based on the instruction. The method may increase cache hit rate and, hence, microprocessor performance.
AI hardwareG06F 12/126
AI classification
AI hardware0.78
Machine learning0.03
Natural language0.01
Evolutionary computation0.00
Knowledge representation0.00
Speech0.00
Vision0.00
Planning0.00
Ownership
INTEL CORPORATION
assignment · 110420167
Assignors
BERKOVITS, ARIEL
On an employer assignment, the assignors are typically the inventors.
From the same owner
DYNAMIC INCLUSIVE AND NON-INCLUSIVE CACHING POLICYUS 12,693,977 · 2026RECOGNITION, REIDENTIFICATION AND SECURITY ENHANCEMENTS USING AUTONOMOUS MACHINESUS 12,694,657 · 2026DEPTH AND MOTION ESTIMATIONS IN MACHINE LEARNING ENVIRONMENTSUS 12,694,659 · 2026Apparatus, device, method and computer program for an autonomously acting machine or a computer systemUS 12,686,127 · 2026Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page MigrationUS 12,688,146 · 2026Generating Pretrained Sparse Student Model for Transfer LearningUS 12,688,422 · 2026OUT-OF-DISTRIBUTION DETECTION USING A NEURAL NETWORKUS 12,688,676 · 2026METHODS AND APPARATUS TO DETECT A REGION OF INTEREST BASED ON VARIABLE RATE SHADINGUS 12,689,741 · 2026