SYSTEM, METHOD AND APPARATUS FOR ALLOCATING HARDWARE RESOURCES USING PSEUDORANDOM SEQUENCES

Patent №

US 7,107,434

Granted

2006-09-12

Filed 2000

Owner

BOARD OF REGENTS THE UNIVERSITY OF TEXAS SYSTEM

+2 more

Lab

—

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09741616

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The present invention provides a system, method and apparatus for allocating resources by assigning resource identifiers to processor resources using at least a portion of a pseudorandom sequence. One or more resource identifiers are generated using at least a portion of each a pseudorandom sequence. Each resource identifier corresponds to one of the resources. One or more of the resource identifiers are then selected for allocation to the instruction.

AI hardwareG06F 9/5011G06F 9/3836G06F 9/384G06F 9/3854G06F 9/3856G06F 9/3858G06F 2209/507

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AI hardware1.00

Planning0.06

Machine learning0.04

Knowledge representation0.01

Natural language0.00

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Speech0.00

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Ownership

BOARD OF REGENTS THE UNIVERSITY OF TEXAS SYSTEM

assignment · 159330109

BOARD OF REGENTS, THE UNIVERSITY OF TEXAS

assignment · 160890218

INTELLECTUAL VENTURES HOLDING 40 LLC

assignment · 209190467

Assignors

JOHN, LIZY KURIAN, SRINIVASAN, SRIVATSAN, JOHN, LIZY KURIAN, SRINIVASAN, SRIVATSAN

On an employer assignment, the assignors are typically the inventors.

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Cites (9)

AUTONOMOUS DISTRIBUTED INSTRUCTION BOOK CONTROL DEVICEUS 6,038,585 · 2000 UNIFIED MULTI-FUNCTION OPERATION SCHEDULER FOR OUT-OF-ORDER EXECUTION IN A SUPERSCALAR PROCESSORUS 5,884,059 · 1999 METHOD OF OPERATING A HIGH PERFORMANCE SUPERSCALAR MICROPROCESSOR INCLUDING A COMMON REORDER BUFFER AND COMMON REGISTER FILE FOR BOTH INTEGER AND FLOATING POINT OPERATIONSUS 5,867,683 · 1999 PIPELINE THROUGHPUT VIA PARALLEL OUT-OF-ORDER EXECUTION OF ADDS AND MOVES IN A SUPPLEMENTAL INTEGER EXECUTION UNITUS 5,802,339 · 1998 METHOD AND APPARATUS FOR DYNAMIC ALLOCATION OF MULTIPLE BUFFERS IN A PROCESSORUS 5,778,245 · 1998 PROGRAM EXECUTION CONTROL DEVICE HAVING ADDRESSABILITY IN ACCORDANCE WITH M SERIES PSEUDO-RANDOM NUMBER SEQUENCEUS 5,651,123 · 1997 HIGH PERFORMANCE SUPERSCALAR MICROPROCESSOR INCLUDING A COMMON REORDER BUFFER AND COMMON REGISTER FILE FOR BOTH INTEGER AND FLOATING POINT OPERATIONSUS 5,651,125 · 1997 PSEUDO-RANDOM SEQUENCE GENERATORSUS 5,323,338 · 1994 Patent US 5,584,037US 5,584,037

Related research

Efficient Dynamic Pinning of Parallelized Applications by Distributed Reinforcement LearningarXiv Possible and Necessary Allocations via Sequential MechanismsarXiv A Heuristic Initialized Memetic Algorithm for the Joint Allocation of Heterogeneous Stochastic ResourcesSemantic Scholar Multi Armed Bandit based Resource Allocation in Near Memory Processing ArchitecturesOpenAlex Sequential Fair Resource Allocation under a Markov Decision Process FrameworkarXiv

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