Patent №
US 7,120,856
Granted
2006-10-10
Filed 2003
Owner
LEANICS CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10670018
A joint code-encoder-decoder design approach and circuit architecture design for (3,k)-regular LDPC coding system implementation. The joint design process relies on a high girth (2,k)-regular LDPC code construction. The decoder realizes partly parallel decoding. The encoding scheme only contains multiplications between sparse matrices and vector and multiplication between a very small dense matrix and vector.
AI classification
AI hardware1.00
Evolutionary computation0.00
Knowledge representation0.00
Machine learning0.00
Natural language0.00
Speech0.00
Vision0.00
Planning0.00
Ownership
LEANICS CORPORATION
assignment · 182650936
Assignors
ZHANG, TONG, PARHI, KESHAB K.
On an employer assignment, the assignors are typically the inventors.
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