Patent №
US 7,120,892
Granted
2006-10-10
Filed 2004
Owner
XILINX, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10892613
A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock.
AI classification
Ownership
XILINX, INC.
assignment · 155790523
Assignors
KNOL, DAVID A., RAJE, SALIL RAVINDRA
On an employer assignment, the assignors are typically the inventors.