SYSTEM AND METHOD OF DESIGN FOR TESTABILITY

A system and a method for implementing design for testability is disclosed, in that the method includes the steps of inputting function description data for defining hardware functions represented in the form independent of architecture; recognizing register variables inferable by memory elements, which are contained in the function description data; simulating events induced by affixing random numbers to the register variables; extracting control signals contained in the function description data as extracted control signals; analyzing the results of the simulation with respect to the extracted control signals; inserting test points for control signals having low toggle rates among the extracted control signals; and executing logic synthesis on the control signals having low toggle rates including the test points.