HYBRID CARRY LOOK AHEAD/CARRY SELECT ADDER INCLUDING CARRY LOGIC GENERATING COMPLEMENTARY HOT CARRY SIGNALS, AND METHOD FOR PRODUCING THE CARRY LOGIC

A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry signals. In a method for producing a carry logic circuit, a group generate logic function GI, I+1=GI OR GI+1 AND PI is to be performed. When GI+1=CI+1, GI, I+1=CI, arrival times of generate signals GI and GI+1, are investigated. If GI arrives before GI+1, a complex AND-OR-INVERT gate is used, otherwise a cascaded pair of NAND gates is selected. To produce a complementary carry signal, a logic function GI, I+1′=GI′ AND GI+1′ OR PI′ is to be performed. If the generate signal GI′ arrives before GI+1′, a complex OR-AND-INVERT gate is used, otherwise a cascaded pair of NOR gates is selected.