Patent №
US 7,277,992
Granted
2007-10-02
Filed 2005
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11087916
A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.
AI classification
AI hardware1.00
Planning0.07
Knowledge representation0.00
Speech0.00
Machine learning0.00
Evolutionary computation0.00
Natural language0.00
Vision0.00
Ownership
INTEL CORPORATION
assignment · 163610775
Assignors
SHANNON, CHRISTOPHER J., ROWLAND, MARK, SRINIVASA, GANAPATI
On an employer assignment, the assignors are typically the inventors.
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