Patent US 9,684,595

Patent №

US 9,684,595

Granted

—

Owner

—

Lab

—

AI components

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

15162707

A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

AI hardwareG06F 12/0811G06F 12/0804G06F 12/0831G06F 12/0837G06F 12/0891G06F 2212/283G06F 2212/621

Google Patents

AI classification

AI hardware0.90

Planning0.03

Knowledge representation0.00

Natural language0.00

Machine learning0.00

Evolutionary computation0.00

Vision0.00

Speech0.00

Cites (19)

TECHNIQUE AND APPARATUS FOR IDENTIFYING CACHE SEGMENTS FOR CACHING DATA TO BE WRITTEN TO MAIN MEMORYUS 8,266,385 · 2012 RECONFIGURABLE CACHEUS 8,230,176 · 2012 SYNCHRONIZING RECENCY INFORMATION IN AN INCLUSIVE CACHE HIERARCHYUS 7,757,045 · 2010 CACHE EVICTION TECHNIQUE FOR REDUCING CACHE EVICTION TRAFFICUS 7,277,992 · 2007 METHOD AND MECHANISM TO USE A CACHE TO TRANSLATE FROM A VIRTUAL BUS TO A PHYSICAL BUSUS 7,032,074 · 2006 CACHE INVALIDATION BUS FOR A HIGHLY SCALABLE SHARED CACHE MEMORY HIERARCHYUS 6,826,654 · 2004 APPARATUS FOR IMPRECISELY TRACKING CACHE LINE INCLUSIVITY OF A HIGHER LEVEL CACHEUS 6,826,655 · 2004 LOCAL INVALIDATION BUSES FOR A HIGHLY SCALABLE SHARED CACHE MEMORY HIERARCHYUS 6,813,694 · 2004 METHOD AND MECHANISM TO USE A CACHE TO TRANSLATE FROM A VIRTUAL BUS TO A PHYSICAL BUSUS 6,721,848 · 2004 PERFORMANCE IMPROVEMENT OF A WRITE INSTRUCTION OF A NON-INCLUSIVE HIERARCHICAL CACHE MEMORY UNITUS 6,715,040 · 2004 EFFICIENT INSTRUCTION CACHE COHERENCY MAINTENANCE MECHANISM FOR SCALABLE MULTIPROCESSOR COMPUTER SYSTEM WITH STORE-THROUGH DATA CACHEUS 6,662,275 · 2003 MERGED VERTICAL CACHE CONTROLLER MECHANISMUS 6,347,363 · 2002 NON-INCLUSIVE CACHE SYSTEM USING PIPELINED SNOOP BUSUS 6,076,147 · 2000 METHOD FOR MAINTAINING MULTI-LEVEL CACHE COHERENCY IN A PROCESSOR WITH NON-INCLUSIVE CACHES AND PROCESS IMPLEMENTING THE SAMEUS 6,065,098 · 2000 NON-INCLUSIVE CACHE METHOD USING PIPELINED SNOOP BUSUS 6,061,766 · 2000 HIGH LEVEL (L2) CACHE AND METHOD FOR EFFICIENTLY UPDATING DIRECTORY ENTRIES UTILIZING AN N-POSITION PRIORITY QUEUE AND PRIORITY INDICATORSUS 5,963,978 · 1999 DATA PROCESSING SYSTEM AND METHOD FOR MAINTAINING COHERENCY BETWEEN HIGH AND LOW LEVEL CACHES USING INCLUSIVE STATESUS 5,926,830 · 1999 REDUCING CACHE MISSES BY SNARFING WRITEBACKS IN NON-INCLUSIVE MEMORY SYSTEMSUS 5,909,697 · 1999 Patent US 7,475,193US 7,475,193

Related research

Reinforcement Learning-Based Cache Replacement Policies for Multicore ProcessorsSemantic Scholar Adaptive Caching Policies for Chiplet Systems Based on Reinforcement LearningSemantic Scholar SCION: Size-aware Policy Orchestration for Nonstationary Object Caches (Long Paper Version)arXiv Examining Cache Handling of the FIVE Method on Multicore SystemsSemantic Scholar CacheQuery: learning replacement policies from hardware cachesOpenAlex

Full text

Google Patents