SYSTEM AND METHOD FOR IMPROVED BRANCH PERFORMANCE IN PIPELINED COMPUTER ARCHITECTURES

A system and method for improved branch performance in pipelined computer architectures is presented. Priority bits are set during code execution that corresponds to an upcoming branch instruction. A priority bit may be associated with a register, a resource, or a microsequencer. An instruction selector compares one or more priority bits with each of a plurality of instructions in order to identify particular instructions to execute that make registers and resources available for an upcoming branch instruction. The instruction selector then prioritizes the identified instructions and the pipeline executes in instructions in the prioritized order.