BITLINE SHIELDING FOR THYRISTOR-BASED MEMORY

Patent №

US 7,319,622

Granted

2008-01-15

Filed 2005

Owner

T-RAM SEMICONDUCTOR, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11174813

Method and apparatus for writing and reading information to and from a memory cell. For a read, a write path is used to electrically shield at least one adjacent bitline from a bitline associated with the memory cell to be read, and the memory cell is read while the at least one adjacent bitline is electrically shielded from the bitline associated with the memory cell being read. For a write, the write path is used to electrically shield at the least one adjacent bitline from a bitline associated with a memory cell to be written to; memory cells coupled to a wordline are read and buffered; and the memory cell is written to while the at least one adjacent bitline is electrically shielded from the writing to the memory cell.

AI hardwareG11C 7/02G11C 5/025G11C 7/12G11C 7/18G11C 2211/5614

AI classification

AI hardware0.98
Machine learning0.04
Natural language0.04
Knowledge representation0.00
Vision0.00
Speech0.00
Evolutionary computation0.00
Planning0.00

Ownership

T-RAM SEMICONDUCTOR, INC.

assignment · 167600264

Assignors

ROY, RICHARD

On an employer assignment, the assignors are typically the inventors.

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