PROGRAMMABLE LOGIC DEVICE MEMORY BLOCKS WITH ADJUSTABLE TIMING

Programmable logic device integrated circuits with adjustable register and memory address decoder circuitry are provided. The integrated circuits contain programmable memory blocks and programmable logic that is configured by a user. Depending on the type of user logic that is implemented by the user, the programmable logic device integrated circuit may have different timing needs for its memory blocks. The adjustable register and memory address decoder circuitry has associated programmable elements that are loaded with configuration data. The configuration data adjusts the timing characteristics of the adjustable register and memory address decoder circuitry to accommodate the user logic. The adjustable register and memory address decoder circuitry may be used to make setup and clock-to-output timing adjustments to optimize a logic design.