Patent №
US 7,363,605
Granted
2008-04-22
Filed 2004
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10857264
A method for analyzing a circuit design identifies a possible noise fault for a timing interval based on a timing analysis of a victim net and at least one aggressor net of the circuit design and determines whether the noise fault is feasible based on a behavioral representation of the victim net and the aggressor net for the timing interval.
PlanningG06F 30/3312
AI classification
Planning0.96
Evolutionary computation0.46
AI hardware0.15
Natural language0.01
Knowledge representation0.01
Machine learning0.00
Speech0.00
Vision0.00
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 151860733
Assignors
KONDRATYEV, ALEX, TSENG, KENNETH, WATANABE, YOSINORI
On an employer assignment, the assignors are typically the inventors.
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