MEMORY WITH A MEMORY CELL COMPRISING A MOS TRANSISTOR WITH AN ISOLATED BODY AND METHOD OF ACCESSING

A dynamic random access memory (DRAM) including memory cells distributed in rows and in columns, each memory cell comprising a MOS transistor with a floating body, the memory comprising circuitry for writing a datum into a determined (i.e. selected) memory cell belonging to a determined (i.e. selected) row and to a determined (i.e. selected) column, wherein the write circuitry comprises circuitry capable of bringing the drains of the memory cells of the determined column to a voltage V1; circuitry capable of bringing the sources of the memory cells of the determined row to a voltage V2; and circuitry capable of bringing the drains of the memory cells of the columns other than the determined column and the sources of the memory cells of the rows other than the determined row to a voltage V3, voltages V1, V2, and V3 being such that |V1−V2|>|V3−V2| and (V1−V2)×(V3−V2)>0.