Patent №
US 7,433,242
Granted
2008-10-07
Filed 2005
Owner
KABUSHIKI KAISHA TOSHIBA
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11297453
A semiconductor memory device includes a semiconductor substrate including a semiconductor layer on a first insulation film; a memory cell including a source and a drain formed in the semiconductor layer, and a floating body region provided between the source and the drain, the memory cell storing data according to an amount of charges accumulated in the floating body region; a second insulation film provided on the floating body region of the memory cell; a word line provided on the second insulation film; a bit line connected to the drain; a source line connected to the source; and a plate electrode electrically insulated from the floating body region by the first insulation film, wherein in at least a part of a period for writing data to the memory cell, a potential of the plate electrode is changed to reduce an absolute value of a threshold voltage of the memory cell.
AI classification
Ownership
KABUSHIKI KAISHA TOSHIBA
assignment · 176910362
Assignors
OHSAWA, TAKASHI
On an employer assignment, the assignors are typically the inventors.