TESTING ADDRESS LINES OF A MEMORY CONTROLLER

Patent №

US 7,526,689

Granted

2009-04-28

Filed 2006

Owner

XILINX, INC.

Lab

—

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11478207

All the address lines in a data processing system can be tested by using one or more small memory device that do not occupy the full addressing capability of the address lines. In one embodiment, some of the address inputs of the memory device is connected to different address lines at different times. Instructions are pre-loaded into some locations of the memory device such that the address lines has to be asserted to fetch the instructions for execution. By executing the instructions and appropriately connecting the address lines to the address input, all the address lines can be tested. In another embodiment, some of the locations are pre-loaded with a set of predetermined values. A program then writes another set of predetermined values to associated locations. By reading the values in the locations and compared with the sets of predetermined values, it is possible to determine if the address lines are functioning properly.

AI hardwareG11C 29/02G11C 29/025

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AI hardware0.54

Machine learning0.00

Planning0.00

Vision0.00

Evolutionary computation0.00

Natural language0.00

Speech0.00

Knowledge representation0.00

Ownership

XILINX, INC.

assignment · 180230367

Assignors

YIN, ROBERT

On an employer assignment, the assignors are typically the inventors.

From the same owner

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Cites (37)

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and 12 more

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