SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE

Decreases in area efficiency and wiring efficiency and degradation in performance are prevented which result from imbalances in dimensional ratios between miniaturized control circuits and other components brought by the development of microfabrication process such as a process of fabricating large-capacity DRAMs as hard macros. A memory array region and a control region are placed such that the two regions are in contact with each other and have a convex shape when viewed from above. Because of this, the layout areas of memories such as large-capacity DRAMs are optimized and their production cost can be reduced. That is, by taking note that the fact that large-capacity DRAMs are in a quadrilateral shape is not an essential condition for the ease of their placement because large-scale DRAMs have the disadvantages that the number of the DRAMs provided in semiconductor devices is limited and the ratio of the areas of the DRAMs to that of the semiconductor devices is high unlike ROMs and SRAMs required to come in various sizes, a large-capacity DRAM can be not only fabricated with its area efficiency and wiring efficiency optimized but provided as a hard macro having a configuration easily laid out in terms of the implementation of a system LSI.