COMPACT CHIP PACKAGE MACROMODELS FOR CHIP-PACKAGE SIMULATION

Patent №

US 7,590,952

Granted

2009-09-15

Filed 2006

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11563704

A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.

AI hardwareG06F 30/3308G06F 30/20G06F 30/367G06F 2113/18H01L 2224/16225H01L 2924/00011H01L 2924/00014H01L 2924/15311+1 more

AI classification

AI hardware0.87
Vision0.01
Evolutionary computation0.00
Natural language0.00
Knowledge representation0.00
Machine learning0.00
Speech0.00
Planning0.00

Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 185550206

Assignors

BEATTIE, MICHAEL W., KRAUTER, BYRON L., ZHENG, HUI

On an employer assignment, the assignors are typically the inventors.

From the same owner

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