WAVESCALAR ARCHITECTURE HAVING A WAVE ORDER MEMORY

Patent №

US 7,657,882

Granted

2010-02-02

Filed 2005

Owner

UNIVERSITY OF WASHINGTON

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11041396

A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

AI hardwareG06F 9/5033G06F 9/3004G06F 9/30087G06F 9/3842G06F 9/3851G06F 9/4494G06F 9/5016G06F 9/5038+6 more

AI classification

AI hardware1.00
Evolutionary computation0.01
Natural language0.00
Speech0.00
Vision0.00
Machine learning0.00
Knowledge representation0.00
Planning0.00

Ownership

UNIVERSITY OF WASHINGTON

assignment · 156650374

Assignors

OSKIN, MARK H., EGGERS, SUSAN J., SWANSON, STEVEN J.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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