METHOD FOR THE COMPUTER-AIDED ASCERTAINMENT OF A CLOCK TREE STRUCTURE, AND INTEGRATED SEMICONDUCTOR CIRCUIT

A method for the computer-aided ascertainment of a clock tree structure which couples a clock generation unit to a multiplicity of switching elements ascertains first switching elements from the multiplicity of switching elements, the first switching elements infringing a prescribed, first time-based switching criterion. In further method steps, the first switching elements are linked to the clock generation unit, and a first buffer element is inserted between the clock generation unit and the first switching elements. An integrated semiconductor circuit has a multiplicity of switching elements which are coupled to a clock generation unit via a clock tree structure. It also has a multiplicity of first switching elements which infringe a time-based switching criterion, which multiplicity is ascertained from the multiplicity of switching elements. A buffer element is inserted into the clock tree structure between the clock generation unit and the first switching elements.