PARTITIONING ELECTRONIC CIRCUIT DESIGNS INTO SIMULATION-READY BLOCKS

A partitioning method for an integrated circuit (IC) design includes providing a textual file representing the design as library-specific cells and interconnections, including timing data for the cells and timing data derived from the design after placement and routing. The design is flattened to cell level. Edge-triggered flip-flops (ETFF's) are selected and divided into two groups by communications attributes. First group is subdivided into the number of subsets in the partition. The ETFF's in each subset are analyzed by their communications attributes, and divided into those that connect to circuit elements outside the particular subset, and those that do not, reducing intersubset communications and placing them under external clock control. The partition is electrically equivalent to the design. The design is simulated by placing each subset on its own computer with simulator software. The computers are interconnected. User interventions may be allowed. Results from simulations are collected, merged, and presented.