SYSTEM AND METHOD FOR IMPLEMENTING A SOFTWARE-SUPPORTED THREAD ASSIST MECHANISM FOR A MICROPROCESSOR

A system and computer-implementable method for implementing software-supported thread assist within a data processing system, wherein the data processing system supports processing instructions within at least a first thread and a second thread. An instruction dispatch unit (IDU) places the first thread into a sleep mode. The IDU separates an instruction stream for the second thread into at least a first independent instruction stream and a second independent instruction stream. The first independent instruction stream is processed utilizing facilities allocated to the first thread and the second independent instruction stream is processed utilizing facilities allocated to the second thread. In response to determining a result of the processing in the first independent instruction stream requires write back to registers allocated to the second thread, the IDU sets at least one selection bit to enable selective copying of content within registers allocated to the first thread to registers allocated to the second thread.