METHOD AND APPARATUS FOR AIDING VERIFICATION OF CIRCUIT, AND COMPUTER PRODUCT

A verification aiding apparatus includes an acquiring unit that acquires implementation description information of a verification target circuit, and a classifying unit that classifies registers in the verification target circuit for each type of processing for each command executable by the verification target circuit. Thus, implementation description classification information can be obtained. A setting unit performs a verification priority setting process and a generating unit performs a sequential command generating process, and a sequential command is output.