A CMOS IMAGE SENSOR HAVING A THIRD FET DEVICE WITH THE GATE TERMINAL COUPLED TO THE DIFFUSION REGION OF A FIRST FET DEVICE, THE SECOND TERMINAL COUPLED TO A COLUMN SIGNAL LINE, AND THE FIRST TERMINAL COUPLED TO A ROW SELECT SIGNAL

A design structure for a CMOS image sensor and active pixel cell design that provides an output signal representing an incident illumination light level that is adapted for time domain analysis. Thus, the noise sources associated with charge integration and the contribution of dark current to it, is avoided. The active pixel cell design implements only three FETs: a transfer device, a reset device and an output transistor device having one diffusion connected to a Row Select signal. In this mode of operation, use is made of the voltage decay at the photo diode to generate a pixel output at one diffusion of the output transistor device, which is a pulse with fixed amplitude independent of the incident illumination level. For use of an NFET output transistor device, the pulse width is an inverse function of the incident illumination level. For a PFET output transistor device, the output pulse has a time delay, from a reference signal, by an amount that is an inverse function of the incident illumination level.