METHOD AND SYSTEM FOR UNFOLDING/REPLICATING LOGIC PATHS TO FACILITATE MODELING OF METASTABLE VALUE PROPAGATION
Patent №
US 7,870,528
Granted
2011-01-11
Filed 2008
Owner
—
Lab
—
AI components
1
hardware
Assignment
None on record
Dataset
AIPD
2023_r1 edition
Application
12168793
A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive latch to sinks of the net. The paths are unfolded by replicating combinational logic and wiring along the coincident portions to form non-intersecting, separate paths from the receive latch to two or more sinks. Common data or control inputs are provided for the gates in the replicated combinational logic. Driver logic may additionally be inserted along each replicated path, upstream of the combinational logic, to independently drive each of the sinks.