VECTOR SEQUENCE SIMPLIFICATION FOR CIRCUIT VERIFICATION

One set of illegal vector sequences is manually generated for a circuit design and a symbolic simulator is used to automatically generate another set of illegal vector sequences for the circuit design. For verification purposes, the relationship between the manually generated set and the automatically generated set is determined. Prior to determining this relationship, one or both of the sets are simplified. One simplification technique includes replacing pairs of illegal vector sequences that are the same except at one bit position with a more general illegal vector sequence representative of both illegal vector sequences of the pair. Another simplification technique includes sorting the illegal vector sequences in a list having a sort order from most general to most specific and then identifying illegal vector sequences that are redundant in view of one or more other illegal vector sequences prior in the sort order based on a binary decision diagram (BDD)-based analysis that sequences through the sorted list in its sort order.