Patent №
US 8,020,125
Granted
2011-09-13
Filed 2008
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
4
ml · kr · planning · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
12208234
A method and apparatus for producing a verification of digital circuits is provided. In an exemplary embodiment, a set of Boolean and Integer constraints are derived, and a set of Boolean and Integer stimuli are generated that meet the constraints. These stimuli are then used to verify a digital design, and a verification report is generated. In other example embodiments, a computing apparatus and computer software product are provided. The computer software product containing a set of executable instructions that, when executed, configure the computing apparatus to produce a verification report by the provided methods.
AI classification
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 215100111
Assignors
KUEHLMANN, ANDREAS, KITCHEN, NATHAN
On an employer assignment, the assignors are typically the inventors.