Patent №
US 8,041,881
Granted
2011-10-18
Filed 2007
Owner
METARAM, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11762010
A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
AI classification
AI hardware0.50
Natural language0.00
Evolutionary computation0.00
Planning0.00
Machine learning0.00
Speech0.00
Vision0.00
Knowledge representation0.00
Ownership
METARAM, INC.
assignment · 194220468
Assignors
RAJAN, SURESH NATARAJAN, SCHAKEL, KEITH R., SMITH, MICHAEL JOHN SEBASTIAN, WANG, DAVID T., WEBER, FREDERICK DANIEL
On an employer assignment, the assignors are typically the inventors.
From the same owner
CONFIGURABLE MEMORY CIRCUIT SYSTEM AND METHODUS 10,013,371 · 2018CONFIGURABLE MEMORY CIRCUIT SYSTEM AND METHODUS 9,171,585 · 2015POWER MANAGEMENT OF MEMORY CIRCUITS BY VIRTUAL MEMORY SIMULATIONUS 8,972,673 · 2015SIMULATING A MEMORY CIRCUITUS 8,949,519 · 2015MEMORY CIRCUIT SYSTEM AND METHODUS 8,868,829 · 2014SIMULATING A MEMORY STANDARDUS 8,745,321 · 2014EMULATION OF ABSTRACTED DIMMS USING ABSTRACTED DRAMSUS 8,631,193 · 2014MEMORY MODULES WITH RELIABILITY AND SERVICEABILITY FUNCTIONSUS 8,615,679 · 2013