DIVERSITY COMBINING ITERATIVE DECODER

An iterative decoder circuit includes an N number of sub-decoders, N−1 of the sub-decoders each being responsive to a baseband signal from one of M number of signal processing circuits. Each of the N−1 number of sub-decoders includes, an inner delay responsive to a baseband signal provided by a corresponding signal processing circuit for generating an inner delayed signal, a modified decoder that receives the inner delayed signal and generates a set partition signal, some of which have less errors than previous set partition signals. An Nth inner delay is responsive to the baseband signal and provides an Nth inner delayed signal. An Nth modified decoder is responsive to the Nth inner delayed signal and to the set partition signal and provides an output signal, wherein the probability of error of the output signal is reduced by correcting errors in some of the set partition signals.