METHOD FOR BOUNDED TRANSACTIONAL TIMING ANALYSIS

A portion of a gate-level netlist representing an integrated circuit design is selected for optimization. A timing window representing the selected portion is made comprising one or more copies of the selected portion. A checkpoint is created for the timing window and stored in a transaction history. One or more changes are then made to the timing window and stored in the transaction history. The changed elements are marked as dirty and stored in the transaction history. After the one or more changes have been made, the timing window is queried for current timing conditions and compared with the checkpoint. If the one or more changes are an improvement, the one or more changes are committed by replicating the one or more changes to the portion of the gate-level netlist. If the one or more changes are not an improvement, the timing window may be restored to the checkpoint.