CACHE COHERENCY PROTOCOL WITH BUILT IN AVOIDANCE FOR CONFLICTING RESPONSES

Patent №

US 8,250,308

Granted

2012-08-21

Filed 2008

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12031977

The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership state of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.

AI classification

AI hardware1.00
Planning0.38
Natural language0.02
Evolutionary computation0.01
Knowledge representation0.01
Speech0.00
Machine learning0.00
Vision0.00

Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 205160165

Assignors

PAPAZOVA, VESSELINA K., AMBROLADZE, EKATERINA M., BLAKE, MICHAEL A., MAK, PAK-KIN, O'NEILL, ARTHUR J., JR., WALTERS, CRAIG R.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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