CENTRAL REPOSITORY FOR WAKE-AND-GO MECHANISM

Patent №

US 8,312,458

Granted

2012-11-13

Filed 2008

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12024384

A wake-and-go mechanism is provided with a central repository wake-and-go array for a multiple processor data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread running on a processor within the multiple processor data processing system is waiting for an event. The wake-and-go mechanism updates a central repository wake-and-go array with a target address associated with the event. Each entry in the central repository wake-and-go array may include a thread identification (ID), a central processing unit (CPU) ID, the target address, the expected data, a comparison type, a lock bit, a priority, and a thread state pointer, which is the address at which the thread state information is stored.

AI hardwareG06F 9/52G06F 9/542

AI classification

AI hardware0.87
Planning0.15
Natural language0.00
Evolutionary computation0.00
Vision0.00
Machine learning0.00
Knowledge representation0.00
Speech0.00

Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 204600677

Assignors

ARIMILLI, RAVI K., SHARMA, SATYA P., SWANBERG, RANDAL C.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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