Patent №
US 8,453,079
Granted
2013-05-28
Filed 2009
Owner
—
Lab
—
AI components
1
hardware
Assignment
None on record
Dataset
AIPD
2023_r1 edition
Application
12550582
Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a synchronous circuit design. The synchronous netlist may include combinational logic gates and state-holding elements. The synchronous netlist may be converted to an asynchronous circuit design. The converting may include grouping the combinational logic gates by operations into functions.