TRANSLATED MEMORY PROTECTION

Patent №

US 8,495,337

Granted

2013-07-23

Filed 2010

Owner

Lab

AI components

1

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

12762187

A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

AI hardwareG06F 9/3808G06F 9/3812G06F 9/45504G06F 13/4239

AI classification

AI hardware0.99
Planning0.15
Speech0.00
Natural language0.00
Evolutionary computation0.00
Machine learning0.00
Vision0.00
Knowledge representation0.00
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