INTERUPT VECTORING FOR TRACE EXCEPTION FACILITY IN COMPUTER SYSTEMS

Patent №

US 5,963,737

Granted

1999-10-05

Filed 1996

Owner

INTERNATIONAL BUSINESS MACHINES COROPORATION

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

08634467

An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler. Only the code which is used to save state and check to see if an exception is registered is in the kernel, and this part of the exception handling code is implementation-independent. i.e., the same for all implementations of this processor architecture.

AI hardwareG06F 9/32G06F 11/3466

AI classification

AI hardware0.99
Evolutionary computation0.37
Planning0.01
Natural language0.01
Vision0.01
Speech0.01
Knowledge representation0.00
Machine learning0.00

Ownership

INTERNATIONAL BUSINESS MACHINES COROPORATION

assignment · 79590282

Assignors

MEALEY, BRUCE G., VAN FLEET, JAMES W., WILLIAMS, MICHAEL S.

On an employer assignment, the assignors are typically the inventors.

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