PLANNING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION

Methods, systems, and computer program products may provide planning for hardware-accelerated functional verification in data processing systems. A method may include receiving, by a computer system, a description of architecture of a hardware accelerator for accelerating functional verification of a circuit design, the architecture including a plurality of logical processors. The method may additionally include receiving, by the computer system, a description of the circuit design having a plurality of gates, and representing, by the computer system, each gate, each stage of the functional verification, and each logical processor as a separate object based on the received description of the architecture and the circuit design. The method may further include representing, by the computer system, relationships between gates as pairwise edges, and defining, by the computer system, a goal state that requires each gate to be scheduled for execution by a logical processor during a stage of the functional verification.