Patent №
US 8,612,950
Granted
2013-12-17
Filed 2008
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
12142102
A method and apparatus for dynamic optimization of strong atomicity barriers is herein described. During runtime compilation, code including non-transactional memory accesses that are to conflict with transactional memory accesses is patched to insert transactional barriers at the conflicting non-transactional memory accesses to ensure isolation and strong atomicity. However, barriers are omitted or removed from non-transactional memory accesses that do not conflict with transactional memory accesses to reduce barrier execution overhead.
AI classification
Ownership
INTEL CORPORATION
assignment · 220970813
Assignors
SHPEISMAN, TATIANA, MENON, VIJAY, ADL-TABATABAI, ALI-REZA
On an employer assignment, the assignors are typically the inventors.