UNIFIED OPTIMISTIC AND PESSIMISTIC CONCURRENCY CONTROL FOR A SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEM
Patent №
US 9,052,947
Granted
2015-06-09
Filed 2013
Owner
INTEL CORPORATION
Lab
—
AI components
2
planning · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
14028018
A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
AI classification
Ownership
INTEL CORPORATION
assignment · 351260353
Assignors
ADL-TABATABAI, ALI-REZA, BACH, MOSHE, BERKOWITS, SION, COWNIE, JAMES HENRY, NI, YANI, OLIVIER, JEFFREY V., SAHA, BRATIN, TAL, ADY, WELC, ADAM
On an employer assignment, the assignors are typically the inventors.